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by W.A. Steer  PhD
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Homebuilt video digitiser MkII

A "video-digitiser" (also known as a "frame grabber") captures still frames from a TV set, video camera, or video recorder, etc., and forwards them to a computer for display, storage, or general manipulation. This document describes the MarkII version of a home-built digitiser which interfaces to an EPP parallel port on IBM PCs. MkII supports colour captures (PAL/NTSC decoding in software).

Note: the Bt218 chip, around which this project is based, ceased to be manufactured during the year 2000. If you want to build this project as shown, ensure you can get some old stock! Alternatively, you could adapt the circuit to work with a different low-cost ADC, such as the TDA8703 from Philips. I have not done this myself yet, so cannot offer details.

You might also want to check out my earlier (Mk1) digitiser page, which includes more background information, particularly on video signals and timing.

MkII Video digitiser - Specification

Any PC hardware capable of running the operating systems mentioned should run the software adequately, though as always, a faster PC will often result in better performance. In particular, colourisation will be very slow on anything sub-Pentium! An EPP-type parallel port is required (though with software modifications, a simple bi-directional port would be useable, with poorer speed)

The principal improvements over Mk I are

Limitations: Notes:
Captured image
Example colourised image, digitised, I think, from ITV's Cook Report programme, 7th February 1999. Off-air from the Crystal Palace transmitter, London.
(This image is from only one field, so the height needs to be doubled to obtain the correct aspect ratio). It was digitised with a 14.161Msps clock, partially phase-locked to the line-sync.

Prototype digitiser
Digitiser in prototyping (image from b&w TV camera, captured by the very hardware featured)


Block diagram and overall description

Block diagram

The ADC converts the incoming composite video signal to a digital representation, sampled typically at 15MHz. This data rate is far too fast for the parallel port to cope with directly, so instead the circuitry is arranged so that data from ADC is fed into a high-speed 256kB field memory. Video timing logic uses line and field synchronisation signals from the sync-separator to ensure that storage begins and ends at field boundaries, and that a fixed number of samples (pixels) are collected for each video scan line. PC parallel port interface logic controls the output of data from the field memory to the host PC, and temporarily halts the refreshing of the image in the memory while data is being read out.

(see the original digitiser page for discussion of composite video signals)

Detailed circuitry

Table of ICs

IC 1EL4581CNVideo sync separatorElantec (near-equiv from National)
IC 274HC14Hex Schmitt inverting bufferTexas/National/Motorola
IC 328.322MHz osc.Quartz oscillator moduleAEL / EuroQuartz* see text for alternatives
IC 474HC404012-bit async. binary counterTexas/National/Motorola* dependent on clock arrangement
IC 574HC74Dual 'D' latch with set/resetTexas/National/Motorola
IC 674HC4017Decade counterTexas/National/Motorola
IC 7Bt218KP-2020Msps 8-bit video ADCBrooktree (Rockwell Semiconductor)
IC 8MSM518221A-ZS-30256kB field video memoryOKI semiconductorZIG-ZAG package!
IC 974HC14Hex Schmitt inverting bufferTexas/National/Motorola
IC 1074HC00Quad NAND gateTexas/National/Motorola
IC 1174HC5418-bit data bufferTexas/National/Motorola


For convenience, the circuit is drawn in three sheets: 1) showing the analog and digital video signal path, including parallel port interface, 2) showing the clock and video timing, 3) the voltage regulator.

Errata: In the diagram below, the connection to pin 12 of the Bt218 ADC (clamp input) should come from pin 2 (the output) of inverter IC2a, not from pin 1.

Diagram 1
Diagram 1:Main circuit diagram, showing analog and digital signal paths.

Diagram 2
Diagram 2:Clock, and video timing logic.

Diagram 3
Diagram 3:Power supply.

Points to note:

Sampling clock rates

In practice, any sampling clock rate in the region of 12 to 15MHz will give adequate results. However, various optimisations may be desireable: There are digitiser clock-generator ICs on the market which generate line-locked clocks of all the standard frequencies given a video signal. I did not opt to use one of these owing to the cost, added complexity, and possible difficulty of obtaining supplies.

My design was based on a crystal oscillator of 28.322MHz which I happened to have to hand. When divided by 2, this gives 14.161MHz. Because this clock does not give an integral number of samples per line, a "trick" was used: reset the divide-by-two using the linesyncs - this reduces worst-case jitter down to 0.5pixel, rather than 1pixel. [I would like to try using a 14.750MHz (or 14.000MHz, 14.250MHz) clock free-running (no line-resets), possibly with the crystal trimmed using a variable capacitor to remove all horizontal skewing. This should tidy up the vertical edges and improve colour decoding further... and simplify!]


Since putting this page on line, a couple of minor errors in the circuit diagrams have been reported:

I was going to reproduce the diagrams a little larger and make the corrections, but since the obsolecence of the Bt218KP, this probably won't happen.

Safety and cautionary notes

Legal disclaimer

This video digitiser is a fairly advanced project, and it is therefore assumed that anyone considering building it has some substantial experience of electrical and electronic techniques. I have applied reasonable care in the design and preparation of the circuitry, diagrams and descriptive material, and have endeavoured to point out any particular hazards that might be relevant. Nevertheless, it is always possible that mistakes or omissions have been made: you take ultimate responsibilty for all consequences of building this project.

Specific precautions



A (16-bit) application to capture the images is available: videodig.exe [68kB].
Download, save, and run it. This first release is permanently configured to use the parallel port at base address 0x278 (usually LPT2). It is also permanently set for 840 pixels per line. This program should run on Win31, Win95/98, and WinNT4 platforms.

The complete source code for the above application is also available: vidisrc.zip [10kB].
It was written using the old (Borland) Turbo C++ v3.1 for Windows 3.1 compiler - which will be required to compile it in its entireity.

If you want to write your own software from scratch, the following extracts from my C++ source code should show all the important steps you need to get started.

// Program to collect video-digitised pictures from the EPP parallel port
// Collects ONE FIELD at a time from MSM518221 frame buffer IC.

// (C) W.A.Steer 1998

#define VID_PIX 840          // pixels per line to collect
#define VID_LINES 304        // number of scan lines to collect

const int portbase=0x278;
const int status=portbase+1;
const int control=portbase+2;
const int eppdata=portbase+4;

int scanbuf[VID_PIX/2];  // (16-bit int)

// Initialise port control-output settings (for periods between EPP transfers)

// Commence frame-grab

 // Reset the MSM518221 read-pointer
 outportb(control, 32);
 outportb(control, 36);

 for(int line=0; line<VID_LINES; line++)
  // Get the data
  for(register int dpixel=0; dpixel<(VID_PIX/2); dpixel++)
   scanbuf[dpixel]=inport(eppdata);  // input 2 bytes in one operation

  // store the line in an image bitmap (custom-code)
  image->SetLine(VID_LINES-1-line, (BYTE *)scanbuf);

 // insert code to display image on screen here

Colour decoding [PAL]

See Software PAL/NTSC decoding page. Includes downloadable software!

If you're interested in developing your electronics skills beyond beginner, I can thoroughly recommend you buy 'The Art of Electronics' by Horowitz and Hill. It's an extremely readable hands-on guide to practical electronics and packed with real-world experience and know-how. Widely regarded as the 'bible' of electronics...

<<< Amazon.com   |   Amazon.co.uk >>>

Created: April 1999
Last modified: 12 June 2002

Source: http://www.techmind.org/vd/vidmk2.html

©2000-2001 William Andrew Steer